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Aldec ALINT-PRO 2021.09 | 904.0 mb
Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has launched ALINT-PRO 2021.09 is design rule checking (DRC) tool, which decreases development time dramatically by identifying design issues early in the development schedule.

Release Notes ALINT-PRO 2021.09 Rule Libraries
- New rule added to the ALDEC_BASIC rule plug-in:
. ALDEC_BASIC_VHDL.4013 - Limit the number of characters in one line.
. ALDEC_BASIC_VLOG.4013 - Limit the number of characters in one line.
- Previously, the ALDEC_BASIC_VHDL.1001 rule reported false violation when signal used in range constraint (SPT80129). This is now corrected.
- Previously, the ALDEC_BASIC_VHDL.4210 caused the fatal error in the case with empty files (SPT80385). This is now corrected.
- Previously, the DO254_VHDL.1621 reported a wrong violation for floating static range (SPT80043). This is now corrected.
- Previously, the DO254_VHDL.3611 ignored the ALLOW_NON_OVERLAPPING parameter when scanning subprogram bodies (SPT80019). This is now corrected.
- New rule added to the STARC_VLOG rule plug-in:
. STARC_VLOG. - Do not use loop variables outside of the 'for' loop.
- New rules added to the STARC_VHDL rule plug-in:
. STARC_VHDL. - Do not use generic in the top level of large designs.
. STARC_VHDL. - Specify range when function return type is array.
. STARC_VHDL. - Create latch only blocks and infer latches in these blocks only.
. STARC_VHDL. - Do not use the signal to which a don't-care condition is assigned for the conditional expression of the if statement.
. STARC_VHDL. - Do not use the signal to which a don't-care condition is assigned for the selection expression of case statement that do not assign 'X' in others choice.
. STARC_VHDL. - Do not assign a negative value to an integer.
. STARC_VHDL. - Do not use embedded logic synthesis scripts in the source code.
- Previously, the STARC_VHDL. reported wrong violations for decimal and hexadecimal literals (SPT80139). This is now corrected.
- Previously, the STARC_VHDL. failed if the library function was used (SPT79574). This is now corrected.
Bus Interfaces Detection & Extraction
- ALINT-PRO now supports automatic extraction of user-defined bus interfaces directly from VHDL and Verilog/SystemVerilog RTL descriptions. The interface extraction engine will be used for static and functional verification of industry-standard and user-defined system interconnects.
- Elaboration Viewer enhanced with Interfaces viewing capability.
- New commands are implemented to define user interfaces: interfaces.add, interfaces.remove, interfaces.list
- New command is implemented to report interface instances, extracted from current project : project.interfaces.list
Vendor Libraries
- The following libraries were updated:
. Xilinx Vivado 2020.3.
. Intel Quartus 20.1 (SPT80405).
- Installation modes changed. The custom mode was removed and added the possibility to change the installation configuration..
Design Entry
- Added new message ENTC-1034 in the Parsa phase. It indicates the path to the file that contains the protected code (SPT79956).
- Previously, an internal error used to be reported during the constraint phase when several control generation schemes are detected through the same gate. (SPT80302). This is now corrected.
- Added an option 'Disable RTL/BDD analysis' that disables all RTL/BDD analysis together with all dependent rules. This allows large design synthesis for CDC.
- The set_rdc_false_path command is enhanced with the ability to set rdc false paths between pins/cells/ports (SPT80238).
- Provided an ability to raise compilation message severity using the project.pref.compilationmessageseverity.error command.
- Changed behavior of alintbatch -synthesis option. Now if it is omitted,the report is not generated.
- Added an option Design Entry/Constraints/CDC/'Ignore resets with combinational logic sources'. By default the preference is enabled. When enabled, reset lines with combinational logic source will be omitted during synchronous resets extraction. Two console commands : project.pref.ignorecomblogicresetsources and global.pref.ignorecomblogicresetsources added as well.
- Added Microsemi and Lattice options for Vendor Preset in Create New Workspace wizard.
- Added -vendor_preset option to the workspace.project.create command.
- Added synthesis support for 'real' type signals. This is now synthesized as the nearest integer type signal.
- Added an option Design entry | Elaboration / Synthesis | Synthesis / 'Disable optimization of identical registers' (SPT80613). By default the optimization of identical registers is enabled, causing identical synchronous processes to be synthesized into the single set of register elements. Once enabled, the option preserves all registers generated from identical processes. Two console commands : project.pref.disableoptimizationofidenticalregisters and global.pref.disableoptimizationofidenticalregisters added as well.
- Added an option Linting | 'Wait for license' to enable waiting for available Rules Plugin licenses if they are temporarily in use unaccessible (SPT80678). By default license waiting is disabled, causing an error when licence is unavailable. If the option is enabled ALINT-PRO waits for license during specified in License timeout sec time and then tries to access licenses features with interval specified in Access interval sec option. Two console commands : project.pref.waitforlicense and global.pref.waitforlicense added as well.
- Previously, the command library.generate.blackbox generated design unit name only in lower-case. (SPT80743). This is now corrected and unit name generated with the same letter-case as original.
- Added new console command global.pref.clearconsoleonprojectclean to enabling/disabling the Design entry / Clear Console on project Clean GUI option to clearing the Console window when the project.clean command or workspace.clean command is invoked.
Flow Manager
- Added new phases Constrain Clocks Linting, Constrain Delays Linting, Constrain Resets Linting, Constrain General Linting to Default flow.
× Aldec ALINT-PRO 2021.09 Close
ALINT-PRO is a design verification solution for RTL code written in VHDL, Verilog, and SystemVerilog, which is focused on verifying coding style and naming conventions, RTL and post-synthesis simulation mismatches, smooth and optimal synthesis, correct FSM descriptions, avoiding problems on further design stages, clocks and reset tree issues, CDC, RDC, DFT, and coding for portability and reuse. The solution performs static analysis based on RTL and SDC source files uncovering critical design issues early in the design cycle, which in turn reduces design signoff time dramatically. Running ALINT-PRO before the RTL simulation and logic synthesis phases prevents design issues spreading into the downstream stages of design flow and reduces the number of iterations required to finish the design.

Checking Xilinx Vivado Designs in ALINT-PRO

​Modern Xilinx designs are quite complex and often involve IP blocks. While Vivado can provide basic DRC methodologies and CDC Checks, debugging the results can be difficult. Importing your Xilinx Vivado designs into Aldec's ALINT-PRO would be particularly useful to prevent mistakes in early design stages, and the flow is much quicker as it would avoid low-level synthesis and optimization.​
Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, High-Performance Computing Platforms, Embedded Development Systems, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions.

Product: Aldec ALINT-PRO
Version: 2021.09.1933 *
Supported Architectures: x64
Website Home Page : www.aldec.com
Languages Supported: english
System Requirements: PC **
Size: 904.0 mb

* release info: ALINT-PRO-2021.09-x64.exe

** System Requirements: × Aldec ALINT-PRO 2021.09 Close
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