Cadence Design Systems, Inc. has released an update (HF028) to OrCAD Capture, PSpice Designer and PCB Designer 17.20.000-2016. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.
Fixed CCRs: SPB 17.20.000-2016 HF028
Fixed CCRs: SPB 17.2 HF028
CCRID Product ProductLevel2 Title
1773530 ADW FLOW_MGR DE-HDL hangs on importing components from another design or copying and pasting components within a design
1790584 ADW FLOW_MGR SKILL code for comparing two PCB Editor .brd files does not work in EDM in release 17.2-2016
1794116 ADW FLOW_MGR LRM fails to run on project
1811532 ADW FLOW_MGR The message for missing tools.jar should not appear in adwcopyproject.log
1812109 ADW LRM Library revision manager displays errors while re-importing updated sub-blocks
1771851 ADW PCBCACHE Problem in packaging upreved imported block
1814785 ALLEGRO_EDITOR 3D_CANVAS PCB Editor crashes when a bend is created and then viewed in 3D Viewer
1800131 ALLEGRO_EDITOR DATABASE allegro_downrev_library utility fails on Windows 10
1814558 ALLEGRO_EDITOR DFM Silkscreen checks do not work if silkscreen is defined as mask in cross section
1814607 ALLEGRO_EDITOR DFM DFM check for soldermask does not include Package Geometry/ Soldermask if the soldermask is part of stackup
1813996 ALLEGRO_EDITOR EDIT_ETCH Add Connect crashes PCB Editor if clearance view is set to channel
1810832 ALLEGRO_EDITOR SCHEM_FTB Error while doing Export Physical from DE-HDL to PCB Editor
1811785 ALLEGRO_EDITOR SCHEM_FTB Import > Logic > Import Directory does not resolve the relative path to the packaged folder
1814166 ALLEGRO_EDITOR SCHEM_FTB Error message when exporting design to board using an earlier version of database
1817891 ALLEGRO_EDITOR SCHEM_FTB Error message when exporting design to board using an earlier version
1818954 ALLEGRO_EDITOR SCHEM_FTB Error message when exporting design to board using an earlier version of database
1812808 ALLEGRO_EDITOR SHAPE Artwork is different from PCB board
1814836 ALLEGRO_EDITOR SKILL Doing zcopy Xhatch pattern crashes PCB Editor in release 17.2-2016
1772218 ALLEGRO_EDITOR UI_GENERAL PCB Editor stops responding on Show Element
1778353 ALLEGRO_EDITOR UI_GENERAL Intermittent PCB Editor crashes on loading IDX in release 17.2-2016 Hotfix 020
1818077 ALLEGRO_EDITOR UI_GENERAL axlViewFileCreate disappears behind window or is blank
1807423 ASDA NEW_PROJECT SDA CPM file has erroneous date
1809597 CONCEPT_HDL CORE Problem auditing SI model in Allegro Design Entry HDL from Hotfix 025 onward, no problem in Hotfix 024
1810322 CONCEPT_HDL CORE Unable to package design if OK_NET_ONE_PIN property is set
1813436 CONCEPT_HDL CORE Read-only block import issue in same session: displays error message SPCOCD-553
1813912 CONCEPT_HDL CORE The response in DE-HDL is sometimes extremely slow
1812506 CONCEPT_HDL INTERFACE_DES Error messages during packaging followed by a success message though there are errors in design
1808677 CONSTRAINT_MGR CONCEPT_HDL Auto-generation of differential pair finds several instances of the same net
1808898 CONSTRAINT_MGR CONCEPT_HDL Unable to resolve the ECSet mapping errors if the topology has pin of PINUSE POWER & GROUND
1810320 CONSTRAINT_MGR CONCEPT_HDL DE-HDL - Constraint Manager: Cannot add group to net class if a net in group is a member of the net class
1812459 CONSTRAINT_MGR CONCEPT_HDL Auto-generation of differential pairs has issues
1796234 CONSTRAINT_MGR OTHER PCB Editor crashes on query (ALLOW_ON_ETCH_SUBCLASS) without data type defined
1811692 CONSTRAINT_MGR OTHER Constraint Manager: Set Topology Constraints - Rel Prop Delay - Pins is empty in release 17.2-2016 Hotfix 026
1816311 CONSTRAINT_MGR XNET_DIFFPAIR Extracting a differential pair into SigXplorer crashes DE-HDL
1807593 ORBITIO ALLEGRO_SIP_I Die symbol shifts when importing die from OrbitIO to SiP Layout
1800763 PSPICE SLPS Error while running co-simulation in MATLAB for PSpice-SLPS demo designs
About Allegro and OrCAD 17.2-2016. The OrCAD 17.2-2016 release introduced new capabilities for OrCAD Capture, PSpice Designer, and PCB Designer 17.2-2016 that address challenges with flex and rigid-flex design as well as mixed-signal simulation complexities in IoT, wearables, and wireless mobile devices. This latest release reduces PCB development time by addressing the need to design reliable circuits for smaller, more compact devices.
- OrCAD Flex and Rigid-Flex Technologies
To enable a faster and more efficient flex and rigid-flex design creation critical to IoT, wearables and wireless devices, the OrCAD 17.2-2016 portfolio enables several new capabilities for flex and rigid flex design to minimize design iterations. Key flex and rigid flex features include: Stack-up by zone for flex and rigid-flex designs, Inter-layer checks for rigid-flex designs, Contour and arc-aware routing.
- New Cross-Section Editor
In the OrCAD PCB Designer 17.2-2016 release, the Cross-Section Editor has been redesigned to leverage the underlying spreadsheet technology found in the Constraint Manager. It offers a one-stop shop for features that require the cross section for their setup, such as dynamic unused pad suppression and embedded component design. The Cross-Section Editor has been enhanced to support multiple stackups for rigid-flex design, each capable of supporting conductor and non-conductor layers such as Soldermask and Coverlay.
- New Padstack Editor
A new Padstack Editor has been introduced in OrCAD PCB Editor 17.2-2016 to ease padstack creation through a new modern user interface. In addition to supporting new pad geometries, drill types, additional attributes, and additional mask layers ability to define keep-outs within the padstack with complex geometries for all objects, the new capabilities allow PCB librarians to help PCB designers streamline the design process for complex padstacks, and also the commonly used padstacks.
- OrCAD PCB Designer 17.2-2016 Features
The OrCAD PCB Designer 17.2-2016 release also include new features or enhancements targeted towards improving PCB editors’ productivity and ease-of-use. Other new features include: Via2via Line Fattening (HDI), Display Segments Over Voids, Layer Set Based Routing, Diff Pair Routing and DRC, Full Xnet Support, Gloss Commands, Contour Routing, and many more.
- OrCAD Capture Design Difference Viewer
The Graphical Design Difference Viewer is a powerful, real-time, design difference, visual review utility in OrCAD Capture with the ability to perform logical as well as graphical comparisons on a page-by-page basis. The Graphical Design Difference Viewer generates an interactive single-report HTML file that is platform and tool independent, a unique viewing feature to identify the differences leading to changes in circuit behavior as well as differences based on individual object level, thereby helping address the specialized needs of the users.
- Advanced Annotation
With the newly introduced Advanced Annotation feature supported by OrCAD Capture, users can assign reference ranges hierarchically by automatically assigning values and perform annotation on the whole design, on hierarchy block at any level, page and property block, giving them complete control over their component annotation process in the design cycle.
- PSpice Virtual Prototyping
The new virtual prototyping functionality introduced in PSpice helps electrical engineers overcome design challenges by automating the code generation for multi-level abstraction models written in C/C++ and SystemC. This functionality assists them in generating code requiring limited coding capabilities by design engineers and thereby making the process of virtual prototyping extremely convenient and easy.
Note: The ADW product line, individual ADW products, and product family names have been rebranded in release 17.2-2016. The Allegro Design Workbench (ADW) is now referred to as Allegro Engineering Data Management (EDM). For the full list of new and improved features, and fixed bugs please refer to the release notes located
About Hot-Fix. A Hot-Fix enables a customer to receive fixes for urgent problems, without having to wait for the next service pack. Unlike Service Packs (SP), which are scheduled, periodic releases, Hot-Fix releases are not periodically scheduled. Simply requesting a Hot-Fix does not automatically guarantee that the customer will receive it: all Hot-Fix requests first must be approved and accepted by Cadence prior to delivery. Furthermore, a Hot-Fix may contain fixes related to problems reported earlier by different customers. All the files included in the Hot-Fix will nevertheless be installed.
About Cadence. Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.
Product: Cadence Allegro and OrCAD (Including EDM)
Version: 17.20.000-2016 HF028
Supported Architectures: x64
System Requirements: PC
Supported Operating Systems: Windows 7even or newer / 2008 Server R2 / 2012 Server
System Requirements: Cadence Allegro and OrCAD (Including EDM) version 17.20.000-2016 and above
Download File Size:1.6 GB